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| circuit technology eroflex circuit technology - advanced multichip modules ? 1/8/97 general description the act?f2m32 is a high speed, 64 megabit cmos flash multichip module (mcm) designed for full temperature range military, space, or high reliability applications. the act-f2m32 consists of four high performance 16 mbit (16,777,216 bit) memory die. each die is organized as 2 mbyte (2,097,152 bytes) by 8 bits with thirty-two, 64k byte (65,536 byte) blocks. the products are designed for operation over the temperature range of -55c to +125c and under the full military environment. a desc standard military drawing (smd) number is pending. the act-s512k32 is manufactured in aeroflex?s 80,000 square foot mil-prf-38534 certified facility in plainview, n.y. features 2mx8 2mx8 2mx8 2mx8 ce 4 a 0 ? a 20 i/o 0-7 i/o 8-15 i/o 16-23 i/o 24-31 8 8 8 8 ce 3 we ce 1 ce 2 oe rp wp pin description i/o 0-31 data i/o wp write protect a 0?20 address inputs v c c power supply we write enable v p p program/erase supply ce 1-4 chip enables gnd ground oe output enable nc not connected reserved for further expansion rp reset/pwrdown block diagram ? pga type package(p1) & cqfp(f1) n 4 low power 2m x 8 flash die in one mcm package n organized as 2m x 32 l user configurable to 4m x 16 or 8m x 8 n ttl and cmos compatible inputs and outputs n access times of 80, 100 and 120ns n +12v only programing, +5v 10% supply n 100,000 erase/program cycles n low power dissipation l 8 ma cmos standby current typical n sector architecture (each die) l 32 equal sectors of 64k bytes per each 2m x 8 chip l two step sequence of erase ensures that memory contents are not accidently erased n pipeline command execution n write during erase n industry standard pinouts n packaging ? hermetic ceramic l 68 lead, 1.56" x 1.56" x .140" low profile cqfp, aeroflex code# "f1" l 66 pin, 1.38" x 1.38" x .245" pga type, aeroflex code# "p1" n automated byte write and block erase l command user interface l compatible status register (csr) l global status register (gsr) l 32 block status registers (bsrs) per die n mil-h-38534 compliant mcms available n decoupling capacitors and multiple grounds for low noise n industrial and military temperature ranges act?f2m32 high speed 64 megabit flash multichip module
aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 2 absolute maximum ratings parameter range units storage temperature range -65 to +150 c voltage on any pin with respect to ground (except v c c and v p p ) (2) -2.0 to +7.0 v v p p program voltage with respect to ground during block erase/byte write (2,3) -0.2 to +14.0 v vcc supply voltage with respect to ground (2) -0.2 to +7.0 v notes: 1. minimum dc input voltage is -0.5v. during transitions, inputs may undershoot to -2.0v for periods less than 20ns. maximum dc voltage on output pins is vcc + 0.5v, which may overshoot to vcc + 2.0v for periods less than 20ns. 2. maximum dc voltage on vpp may overshoot to +14.0v for periods less than 20ns. 3. output shorted for no more than 1 second. no more than one output shorted at one time. notice: stresses above those listed under "absolute maximums rating" may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions symbol parameter minimum maximum units v c c power supply voltage +4.5 +5.5 v v i h input high voltage +2.0 v cc + 0.5 v v i l input low voltage -0.5 +0.8 v t a operating temperature (military) -55 +125 c capacitance (v i n = 0v, f = 1mhz, t a = 25 c) symbol parameter maximum units c a d a 0 ? a 20 capacitance 50 pf c o e oe capacitance 50 pf c c e chip enable capacitance cqfp(f1) package 20 pf pga(p1) package 20 pf c w e write enable capacitance 50 pf c i / o i/o 0 ? i/o 31 capacitance 20 pf capacitance guaranteed by design, but not tested. dc characteristics ? cmos compatible (vcc = 5.0v, vss = 0v) parameter sym conditions min max units input leakage current i l i v c c = 5.5v, v i n = v c c to gnd 10 m a output leakage current i l o v c c = 5.5v, v o u t = v c c to gnd 10 m a vcc standby current i c c s v c c = 5.5v, ce = rp = wp = v i n , f = 5mhz 16 ma vcc read current i c c r v c c = 5.5v, ce = v i l , f = 5mhz , i o u t = 0 ma 175 ma vcc write current i c c w write in progress 175 ma vcc block erase current i c c e block erase in progress 60 ma vcc powerdown current i c c d rp = gnd 8 a v p p standby current i p p s v p p < v c c 80 m a v p p powerdown current i p p d rp = gnd 80 m a v p p byte write current i p p w v p p = v p p h , byte write in progress 60 ma v p p block erase current i p p e v p p = v p p h , block erase in progress 60 ma output low voltage v o l v c c = 4.5v, i o l = 5.8 ma 0.45 v output high voltage v o h v c c = 4.5v, i o h = -2.5 ma 2.4 or 0.85v c c v v p p l duringnormal operations v p p l 0.0 6.5 v p p during erase/write operations v p p h 11.4 12.6 v v c c erase/write lock voltage v l k o 2.0 v notes: 1) block erases/byte writes are inhibited when v p p v p p l k . 2) dc test conditions v i l = 0.3v, v i h = v c c - 0.3v aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 3 ac characteristics ? write/erase/program operations ? we controlled (vcc = 5.0v, vss = 0v) parameter symbol jedec standard ?080 min max ?100 min max ?120 min max units write cycle time t a v a v t w c 80 100 120 ns chip enable setup time t e l w l t c e 0 0 0 ns write enable pulse width t w l w h t w p 50 50 50 ns vpp setup time (1) t v p w h t v p s 100 100 100 ns address setup time t a v w h t a s 50 50 50 ns data setup time t d v w h t d s 60 60 60 ns data hold time t w h d x t d h 0 0 0 ns address hold time t w h a x t a h 10 10 10 ns chip enable hold time t w h e h t c h 10 10 10 ns write enable pulse width high t w h w l t w p h 30 50 50 ns duration of byte write operation (1,2,3) t w h q v 1 4.5 4.5 4.5 m s duration of block erase operation (1,2,3) t w h q v 2 0.3 0.3 0.3 sec write recovery before read t w h g l 65 80 80 ns rp high recovery time (1) t p h w l t p s 1 1 1 m s notes: 1. guaranteed by design, not tested. 2. the on-chip write state machine incorporates all byte write and block erase functions and overhead of the flash memory, this includes byte program and verity, block precondition and verify, erase and verity. 3. byte write and block erase durations are measured to completion (csr.7 = 1 ) . v p p should be held at v p p h until determination of byte write/block erase success (csr.3/4/5 = 0). ac characteristics ? write operations, ce controlled (1) (vcc = 5.0v, vss = 0v) parameter symbol jedec standard ?080 min max ?100 min max ?120 min max units write enable cycle time t a v a v t w c 80 100 120 ns write enable setup time t w l e l t w s 0 0 0 ns chip enable pulse width t e l e h t c p 50 50 50 ns v p p setup time (2) t v p e h t v p s 100 100 100 ns address setup to ce going high t a v e h t a s 50 50 50 ns data setup time t d v e h t d s 60 60 60 ns data hold time t e h d x t d h 0 0 0 ns address hold time t e h a x t a h 10 10 10 ns write enable hold time t e h w h t w h 10 10 10 ns chip enable pulse width high t e h e l t e p h 30 50 50 ns duration of byte write programming (2,3) t e h q v 1 4.5 4.5 4.5 m s duration of block erase programming (2,3) t e h q v 2 0.3 0.3 0.3 sec write recovery before read t e h g l 65 80 80 ns rp high recovery to ce low (2) t p h e l t p s 1.0 1.0 1.0 m s notes: 1. chip-select controlled writes: write operations are drive by the valid combination of ce and we . in systems where ce defines the write pulse width (within a longer we timing waveform), all setup, hold and inactive we times should be measured relative to the ce waveform. 2. guaranteed by design, not tested. 3. byte write and block erase durations are measured to completion (csr.7 = 1, ry/ by = 1, v o h ). v p p should be held at v p p h until determination of byte write/block erase success (csr.3/4/5 = 0). aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 4 ac characteristics ? read only operations (vcc = 5.0v, vss = 0v) parameter symbol jedec standard ?080 min max ?100 min max ?120 min max units read cycle time t a v a v t r c 80 100 120 ns address access time t a v q v t a c c 80 100 120 ns chip enable to output valid (1) t e l q v t c e 80 100 120 ns output enable to output valid (1) t g l q v t o e 35 40 45 ns c h i p e n a b l e t o o u t p u t l o w z (2) t e l q x t l z 0 0 0 ns c h i p e n a b l e h i g h t o o u t p u t h i g h z (2) t e l q z t h z 30 35 40 ns output enable to output low z (2) t g h q x t q l z 0 0 0 ns reset to output valid t p h q v t p w h 480 550 620 ns output enable high to output high z (2) t g h q z t d f 30 35 40 ns output hold from addresses, ce or oe change, whichever is first (2) t o h 0 0 0 ns notes: 1. oe may be delayed up to t c e ?t o e after the falling edge of ce without impact on t c e . 2. guaranteed by design, but not tested. aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 5 ac waveform for write?erase?program operations, we controlled figure 2 write byte write or erase setup command power-up standby write valid address & data (byte write) or erase confirm command automated byte write or erase delay read status register data write read array command a i n a i n addresses oe ce data we v p p rp d i n valid srd d i n d i n v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v p p h v p p l t a v a v t a v w h t w h a x t e l w l t w h e h t w h w l t w l w h t w h d x t d v w h t v p w h t w h q v 1,2 t w h g l t p h w l high z i o l parameter typical units input pulse level 0 ? 3.0 v input rise and fall 5 ns input and output timing reference 1.5 v output lead capacitance 50 pf notes: 1) v z is programmable from -2v to +7v. 2) i o l and i o h programmable from 0 to 16 ma. 3) tester impedance z o =75 w. 4) v z is typically the midpoint of v o h and v o l . 5) i o l and i o h are adjusted to simulate a typical resistance load circuit. 6) ate tester includes jig capacitance. i o h to device under test v z ~ 1.5 v (bipolar supply) current source current source c l = 50 pf figure 1 ac test circuit aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 6 figure 4 ac waveform for read operations addresses oe ce data we v c c rp v i h v i l v i h v i l v i h v i l v i h v i l v o h v o l +5.0 v gnd v i h v i l standby vccpower-up device and address selection outputs enabled data valid standby vccpower-down addresses stable valid output t p h q v t a v q v t e l q x t g l q x t e l q v t g l q v t o h t g h q z t e h q z t a v a v high z high z alternate ac waveforms for write operations ? ce controlled figure 3 v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v p p h v p p l addresses oe we data ce v p p rp t w l e l t e h w h t a v a v t a v e h t e h a x t e h q v 1,2 t e h g l t e l e h t e h d x t d v e h high z t p h e l t v p e h write byte write or erase setup command power-up standby valid address & data (byte write) or erase confirm command automated byte write or erase delay read status register data write read array command d i n valid srd d i n d i n t e h e l aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 7 principles of operation the act?2m32 mcm is composed of four (4), sixteen(16) megabit memory chips inside the mcm. chip 1 is distinguished by ce 1 and i/o 1-7 , chip 2 by ce 2 and i/o 8-15 , chip 3 by ce 3 and i/o 16-23 , chip 4 by ce 4 and i/o 24-31 . the act-f2m32 includes write automation to manage write and erase functions. the write state machine allows for 100% ttl?level control inputs; fixed power supplies during block erasure and byte write and minimal processor overhead with ram like interface timings. after initial device powerup the act?f2m32 functions as a read-only memory. manipulation of external memory control pins allow array read, standby and output disable operations. the status register can also be accessed through the command user interface when v p p = v p p l . this same subset of operations is also available when high voltage is applied to the v p p pin. in addition, high voltage on v p p enables successful block erasure and byte writing of the device. functions associated with altering memory contents, byte write, block erase, are accessed via the command user interface and verified through the status register. commands are written using standard microprocessor write timings. command user interface contents serve as input to the write status machine, which controls the block erase and byte write circuitry. write cycles also internally latch addresses and data needed for byte write or block erase operations. interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the blocks. this code is copied to, and executed from, system ram during actual flash memory update. after successful completion of byte write and/or block erase, code/data reads from the device are again possible via the read array command. erase suspend/resume capability allows system software to suspend block erase to read data and execute code from any other block. comparison of act-f1m32 to act-f2m32 a superset of commands have been added to the basic act-f1m32 command set to achieve higher write performance and provide additional capabilities. these new commands and features include: l command queuing capability l automatic data writes during erase l software locking of memory blocks l two-byte successive writes in 8-bit systems l erase all unlocked blocks writing of memory data is performed in either byte or word increments typically within 6 sec, a 33% improvement over the act-f1m32. a block erase operation erases one of the 32 blocks, which is about 65% improvement over the act-f1m32. each block can be written and erased a minimum of 100,000 cycles. systems can achieve 1 million block erase cycles by providing wear leveling algorithms and block retirement. each chip in act-f2m32 incorporates two page buffers of 256 bytes (128 words) each to allow page data writes. this feature can improve a system write performance by up to 4.8 times over previous flash memory devices. all operations are started by a sequence of write commands to the device. three status registers (described in detail later) and a ry/ by output pin provide information on the progress of the requested operation. while the act-f1m32 requires an operation to complete before the next operation can be requested, the act-f2m32 allows queueing of the next operation while memory executes the current operation. this eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. the act-f2m32 can also perform write operations to one block of memory while performing erase of another block. the act-f2m32 provides user selectable block locking to protect code or data. each block has an associated nonvolatile lock-bit which determines the lock status of the block. in addition, the act-f2m32 has a master write protect pin ( wp ) which prevents any modifications to memory blocks whose lock-bits are set. the act-f2m32 contains three types of status registers to accomplish various functions: l a compatible status register (csr) which is 100% compatible with the act-f1m32 flash memory's status register. this register, when used alone. provides a straightforward upgrade capability to the act-f2m32 from a act-f1m32 based design. l a global status register (gsr) which informs the system of command queue status, page buffer status and overall write state machine (wsm) status. l 32 block status registers (bsrs) which provide block specific status information such as the block lock-bit status. command user interface and write automation an on-chip state machine controls block erase and byte write, freeing the system processor for other tasks. after receiving the erase setup and erase confirm commands, the state machine controls block preconditioning and erase, returning progress via the status register on each of the four memory chips in the mcm. qfp options with ry/ by also return progress via the status register for each of the four memory chips. byte write is similarly controlled, after destination address and expected data are supplied. data protection depending on the application, the system designer aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 8 may choose to make the v p p power supply switchable (available only when memory byte writes/block erases are required) or hardwired to v p p h . when v p p = v p p l , memory contents cannot be altered. additionally, all functions are disabled whenever vcc is below the write lockout voltage v l k o or when rp is at v i l . the two step byte write/block erase command user interface write sequence provides additional software write protection. bus operation flash memory reads, erase and writes in system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. read the act?2m32 can be read from any of its blocks, and information can be read from the status register of each chip selected. v p p can be at either v p p l or v p p h . the first task is to write the appropriate read mode command to the command user interface. the device automatically resets to read array mode upon initial device powerup or after exit from deep powerdown. chip enable ce is the device selection control, and when active enables the selected memory device. output enable ( oe) is the data input/output (i/o0-i/o31) direction control, and when active drives data from the select memory onto the i/o bus. rp and we must also be at v i h . figure 4 illustrates read bus cycle waveforms. output disable with oe at a logic high level (v i h ), the device outputs are disabled.output pins (i/o 0-31 ) are placed in a high impedance state. standby ce at a logic high level (v i h ) places the device in a standby mode. standby operation disables much of the device's circuitry and substantially reduces device power consumption. the outputs (i/o 0-31 ) are placed in a high impedance state independent of the status of m. if the device is deselected during block erase or byte write, it will continue functioning and consuming normal active power until the operation is completed. writes writes to the command user interface enable reading of device data. they also control inspection and cleaning of the status register. additionally, when v p p = v p p h , the command user interface controls block erasure and byte write. the contents of the interface register serve as input to the internal state machine. the command user interface itself does not occupy an addressable memory location. the interface register is a latch used to store the command and address and data information needed to execute the command. erase setup and erase confirm commands require both appropriate command data and an address within the block to be erased. the byte write setup command requires both appropriate command data and the address of the location to be written, while the byte write command consists of the data to be written and the address of the location to be written. the command user interface is written by bringing we to a logic low level (v i l ) while ce is low. address and data are latched on the rising edge of we . standard microprocessor write timings are used. refer to ac write characteristics and the ac waveforms for write operation, figures 2 and 3, for specific timing parameters. command definitions when v p p l is applied to the v p p pin of the chip selected, read operations from the status register, or array blocks are enabled. placing v p p h on v p p enables successful byte write and block erase operations as well. device operations are selected by writing specific commands into the command user interface of the chip selected. table 2 defines the act?2m32 commands. read array command upon initial device powerup the device defaults to read array mode. this operation is also initiated by writing ffh into the command user interface. microprocessor read cycles retrieve array data. the device remains enabled for reads until the command user interface contents are altered. once the internal write state machine has started a block erase or byte write operation, the device will not recognize the read array command, until the wsm has completed its operation. the read array command is functional when v p p = v p p l or v p p h . read status register command each chip of the act?2m32 contains a status register which may be read to determine when a byte write or block erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status register command (70h) to the command user interface. after writing this command, all subsequent read operations output data from the status register, until another valid command is written to the command user interface. the contents of the status register are latched on the falling edge of oe or ce , whichever occurs last in the read cycle. oe or ce must be toggled to v i h before further reads to update the status register latch. the read status register command functions when v p p = v p p l or v p p h . clear status register command the erase status and byte write status bits are set to "1"s by the write state machine on each chip and can only be reset by the clear status register command. aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 9 these bits indicate various failure conditions (see table 3). by allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence). the status register may then be polled to determine if an error occurred during that sequence. this adds flexibility to the way the device may be used. additionally, the v p p status bit (csr.3) of the chip selected must be reset by system software before further byte writes or block erases are attempted. to clear the status register, the clear status register command (50h) is written to the command user interface. the clear status register command is functional when v p p = v p p l or v p p h . erase setup/erase confirm commands erase is executed one block at a time, initiated by a two cycle command sequence. an erase setup command (20h) is first written to the command user interface, followed by the erase confirm command (d0h). these commands require both appropriate sequencing and address within the block to be erased to ffh. block preconditioning, erase and verify are all handled internally by the write state machine, invisible to the system. after the two command erase sequence is written to it, the act?2m32 automatically outputs status register data when read (see figure 6; block erase algorithm). the cpu can detect the completion of the erase event by analyzing the output of the wsm status bit of the status register. when erase is completed, the erase status bit should be checked. if erase error is detected, the status register should be cleared. the command user interface remains in read status register mode until further commands are issued to it. this two step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. also, reliable block ensure can only occur when v p p = v p p h . in the absence of this high voltage, memory contents are protected against erasure. if block erase is attempted while v p p = v p p l , the v p p status bit will be set to "1". erase attempts while v p p l < v p p < v p p h produce spurious results and should not be attempted. byte write setup/write commands byte write is executed by a two command sequence. the byte write setup command (40h) is written to the command user interface of the chip selected, followed by a second write specifying the address and data (latched on the rising edge of we ) to be written. the wsm then takes over, controlling the byte write and write verify algorithms internally. after the two command byte write sequence is written to it, the device automatically outputs status register data when read (see figure 5; byte write algorithm). the cpu can detect the completion of the byte write event by analyzing the output of the wsm status bit of the status register. only the read status register command is valid while byte write is active. when byte write is complete, the byte write status bit should be checked. if byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully write to "0"s. the command user interface remains in read status register mode until further commands are issued to it. if byte write is attempted while v p p = v p p l , the v p p status bit will be set to "1". byte write attempts while v p p l < v p p aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 11 table 1 ? bus operations command notes rp ce oe we i/o 0-7 read v i h v i l v i l v i h d o u t output disable v i h v i l v i h v i h high z standby 1 v i h v i l x x high z v i h v i h deep powerdown 1,2 v i l x x x high z write v i h v i l v i h v i l d i n notes: 1. x can be v i l or v i h for control and address pins. 2. rp at gnd 0.2v ensures the lowest deep power-down current. 3. commands for different erase operations. data write operations or lock-block operations can only be successfully completed wh en v p p = v p p h . table 2 ? commands definitions ? compatible mode command notes first bus cycle second bus cycle operation address data operation address data read array write x ffh read aa ad read compatible status register 1 write x 70h read x csrd clear status register 2 write x 50h word/byte write write x 40h write wa wd alternate word/byte write write x 10h write wa wd block erase/confirm write x 20h write ba doh erase suspend/resume write x 80h write x doh address aa = array address ba = block address ia = identifier address wa = write address x = don?t care data ad= array data csrd = csr data id = identifier data wd = write data notes : 1. the csr is automatically available after device enters data write, erase or suspend operations. 2. clears csr 3. csr 4. csr 5. also clears gsr 5 and bsr 5 and bsr 2 bits. see status register definitions table 3 ? commands definitions ? enhanced mode command notes first bus cycle second bus cycle third bus cycle operation address data operation address data operation address data read extend status register 1 write x 71h read ra gsrd bsrd page buffer swap 5 write x 72h read read page buffer write x 75h write pa pd single load to page buffer write x 74h write pa pd sequential single load to page buffer 3,4,6 write x e0h write x bcl write x bch page buffer write to flash 3,6 write x 0ch write a0 bc(l,h) write wa bc(h,l) 3,6 write x 0ch write x wcl write wa wch two byte write write x fbh write a0 wd(l,h) write wa wd(h,l) lock block/confirm write x 77h write ba d0h upload status bits/confirm 2 write x 97h write x d0h upload device information write x 99h write x d0h erase all unlocked blocks/confirm write x a7h write x d0h sleep write x f0h abort write x 80h address ba = block address pa = page buffer address ra = extended register address wa = write address x = don?t care data ad= array data pd = page buffer data bsrd = bsr data gsrd = gsr data wc(l,h) = word count (low, high) bc(l,h) = byte count (low, high) wd(l,h) = write data (low, high) notes : 1. ra can be the gsr address or any bsr address. 2. upon device power-up, all bsr lock-bits come up locked the upload status bits command must be written to reflect the actual l ock-bit status. 3. bch/wch must be at 00h for this produce because of the 256-byle (128 word) page buffer size and to avoid writing the page buf fer contents into more than one 256byte segment within an array block. they are simply shown for future page buffer expandability. 4. pa and pd (whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown. 5. this command allows the user to swap between available page butters (0 or 1). 6. bcl = 00h corresponds to a byte count of 1. similarly, wcl = 00h corresponds to a word count of 1. aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 12 table 4 ? compatible status register wsms ess es dws vpps r r r 7 6 5 4 3 2 1 0 csr.7 = write state machine status 1 = ready 0 = busy csr.6 = erase suspended status 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status 1 = error in block erasure 0 = successful block erase csr.4 = data write status 1 = error in byte write 0 = successful byte write csr.3 = vpp status 1 = vpp low detect; operation abort 0 = vpp ok csr.2?csr.0 = reserved for future enhancements these bits are reserved for future use and should be masked out when polling the status register. notes: 1. the wsms bit must first be checked to determine byte write or block erase completion, before the byte write or erase status bit are checked for success. 2. if the dws and erase status bits are set to "1"s during a block erase attempt, an improper command sequence was entered. clear the csr and attempt the sequence again. 3. the v p p status bit, unlike an a/d converter, does not provide continuous indication of v p p level. the wsm interrogates the v p p level only after the byte write or block erase command sequences have been entered and informs the system it v p p has not been switched on. the v p p status bit is not guaranteed to report accurate feedback between v p p l and v p p h . table 5 ? global status register wsms oss dos dss qs pbas pbs pbss 7 6 5 4 3 2 1 0 gsr.7 = write state machine status 1 = ready 0 = busy gsr.6 = operation suspend status 1 = operation suspended 0 = operation in progress/completed ggr.5 = device operation status 1 = operation unsuccessful 0 = operation successful or currently running gsr.4 = device sleep status (2,3) 1 = device in sleep 0 = device not in sleep matrix 5/4 00 = operation successful or currently running 01 = device in sleep mode or pending sleep 10 = operation unsuccessful 11 = operation aborted gsr.3 = queue status 1 = queue full 0 = queue available gsr.2 = page buffer available status 1 = one or two pages available 0 = no page buffer available gsr.1 = page buffer status 1 = selected page buffer ready 0 = selected page buffer available gsr.0 = page buffer select status 1 = page buffer 1 selected 0 = page buffer 0 selected notes: 1. the wsms bit must first be checked to determine completion of a operation (block lock, suspend, upload status bit, erase or data write), before the appropriate status bit (oss or dos) is checked for success. 2. if the operation currently running, then gsr.7 = 0 3. if device pending sleep, then gsr.7 = 0 4. operation aborted. unsuccessful due to abort command 5. the device contains two page buffers. 6. selected page buffer is currently busy with wsm operation. note: 1. when multiple operations are queued, checking bsr 7 only provides indication of completion for that particular block. gsr 7 p rovides indication when all queued operations are completed. aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 13 table 6 ? block status register bs bls bos boas qs vpps r r 7 6 5 4 3 2 1 0 bsr.7 = block status 1 = ready 0 = busy bsr.6 = block-locp status 1 = block unlocked for write/erase 0 = block locked for write/erase bgr.5 = block operation status 1 = operation unsuccessful 0 = operation successful or currently running bsr.4 = block operation abort status 1 = operation aborted 0 = operation not aborted matrix 5/4 00 = operation successful or currently running 01 = not a valid combination 10 = operation unsuccessful 11 = operation aborted (3) bsr.3 = queue status 1 = queue full 0 = queue available bsr.2 = vpp status 1 = vpp low detect, operation aborted 0 = vpp ok bsr.1?bsr.0 = reserved for future enhancements (4) notes: 1. bs must be checked to determine completion of a n operation (block lock, suspend, erase or data write) before the appropriate status bit (bos,bls) is checked for success. 2. the boas bit will not be set until bsr.7 = 1 3. operation halted via abort command. 4. these bits are reserved for future use, mask them out when polling the bsrs. note: 1. when multiple operations are queued, checking bsr 7 only provides indication of completion for that particular block. gsr 7 p rovides indication when all queued operations are completed. aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 14 bus operations command sequence comments write byte write setup data = 40h (10h) address = byte to be written write byte write data to be written address = byte to be written standby/reset check wsms bit v o h = ready, v o l = busy or ready status register check csr.7 1 = ready, 0 = busy toggle oe or ce to update status register repeat for subsequent bytes full status check can be done after each byte or after a sequence of bytes write ffh after the last byte write operation to reset the device to ready array mode bus operations command sequence comments optional read cpu may already have read status register data in wsm ready polling above standby check csr.3 1 = v p p low detect standby check csr.4 1 = byte write error csr.3 must be cleared, if set during a block erase attempt, before further attempts are allowed by the write state machine. csr.4 is only cleared by the clear status register command, in cases where multiple bytes are written before full status is checked. if error is detected, clear the status register before attempting retry on other error recovery. figure 5 automated byte write algorithm start write 40h (10h) byte address write byte address/data status register data wsm ready ? full status check if desired byte write completed no yes read (see above) byte write successful byte write error v p p range error csr.3 = 0 ? csr.4 = 0 ? no no yes yes full status check procedure aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 15 bus operations command sequence comments write erase setup data = 20h address = within block to be erased write erase data = d0h address = within block to be erased standby/reset check wsms bit v o h = ready, v o l = busy or ready compatible status register check csr.7 1 = ready, 0 = busy toggle oe or ce to update compatible status register repeat for subsequent bytes full status check can be done after each byte or after a sequence of bytes write ffh after the last byte write operation to reset the device to ready array mode bus operations command sequence comments optional read cpu may already have read compatible status register data in wsm ready polling above standby check csr.3 1 = v p p low detect standby check csr.4, 5 both 1 = command sequence error standby check csr.5 1 = block erase error start write 20h, block address write d0h, block address wsm ready ? full status check if desired block erase completed no yes figure 6 automated block erase algorithm full status check procedure yes no suspend erase ? status register data read (see above) block erase successful block erase error v p p range error csr.3 = 0 ? csr.5 = 0 ? no no yes yes command sequence error csr.4,5 = 1 ? yes yes erase suspend loop aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 16 bus operations command sequence comments write erase suspend data = 80h write read status register data = 70h standby/reset read campatible status register check csr.7 1 = ready, 0 = busy toggle oe or ce to update status register standby check csr.6 1 = suspended write read array data = ffh read read array data from block other than that being erased write data = d0h start done reading ? yes figure 7 erase suspend/resume algorithm read status register no write ffh continue erase write boh write 70h csr.7 = 1 ? csr.6 = 1 ? write d0h no no yes yes erase has completed aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 17 pin numbers & functions 66 pins ? pga-type pin # function pin # function pin # function pin # function 1 i/o 8 18 a 15 35 i/o 25 52 a 20 2 i/o 9 19 vcc 36 i/o 26 53 ce 3 3 i/o 10 20 ce 1 37 a 7 54 gnd 4 a 14 21 a 19 38 a 12 55 i/o 19 5 a 16 22 i/o 3 39 v p p 56 i/o 31 6 a 11 23 i/o 15 40 a 13 57 i/o 30 7 a 0 24 i/o 14 41 a 8 58 i/o 29 8 a 18 25 i/o 13 42 i/o 16 59 i/o 28 9 i/o 0 26 i/o 12 43 i/o 17 60 a 1 10 i/o 1 27 oe 44 i/o 18 61 a 2 11 i/o 2 28 a 17 45 v c c 62 a 3 12 rp 29 we 46 ce 4 63 i/o 23 13 ce 2 30 i/o 7 47 wp 64 i/o 22 14 gnd 31 i/o 6 48 i/o 27 65 i/o 21 15 i/o 11 32 i/o 5 49 a 4 66 i/o 20 16 a 10 33 i/o 4 50 a 5 17 a 9 34 i/o 24 51 a 6 dimensions in inches. 1.385 sq 1.000 .600 1.000 .100 .020 .016 .100 .155 .145 1.140 1.150 .025 .245 max pin 56 pin 66 pin 11 pin 1 bottom view .015 .035 "p1"? 1.38" sq pga type package aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 18 pin numbers & functions 68 pins ? cqfp pin # function pin # function pin # function pin # function 1 gnd 18 gnd 35 oe 52 gnd 2 ce 1 19 i/o 8 36 ce 4 53 i/o 23 3 a 5 20 i/o 9 37 a 17 54 i/o 22 4 a 4 21 i/o 10 38 a 18 55 i/o 21 5 a 3 22 i/o 11 39 a 19 56 i/o 20 6 a 2 23 i/o 12 40 a 20 57 i/o 19 7 a 1 24 i/o 13 41 nc 58 i/o 18 8 a 0 25 i/o 14 42 rp 59 i/o 17 9 wp 26 i/o 15 43 v p p 60 i/o 16 10 i/o 0 27 v c c 44 i/o 31 61 v c c 11 i/o 1 28 a 11 45 i/o 30 62 a 10 12 i/o 2 29 a 12 46 i/o 29 63 a 9 13 i/o 3 30 a 13 47 i/o 28 64 a 8 14 i/o 4 31 a 14 48 i/o 27 65 a 7 15 i/o 5 32 a 15 49 i/o 26 66 a 6 16 i/o 6 33 a 16 50 i/o 25 67 we 17 i/o 7 34 ce 2 51 i/o 24 68 ce 3 dimensions in inches. 1.50 1.575 sq max .015 0.800 0.500 (4 sides) pin 61 pin 9 pin 43 pin 27 pin 44 pin 1 (4 sides) 0.200 "f1" ? cqfp single-cavity flat package (16 at .050 4 sides) pin 60 pin 26 pin 10 .140 max .010 .050 .005 aeroflex circuit technology f2m32-b 1/8/97 plainview ny (516) 694-6700 19 ordering information model number desc part number speed package act?f2m32n?080p1m 5962?tbd 80ns plug-in act?f2m32n?100p1m 5962?tbd 100ns plug-in act?f2m32n?120p1m 5962?tbd 120ns plug-in act?f2m32n?080f1m 5962?tbd 80ns cqfp act?f2m32n?100f1m 5962?tbd 100ns cqfp act?f2m32n?120f1m 5962?tbd 120ns cqfp circuit technology part number breakdown \\\ act? f 2m 32 n? 020 f1 m aeroflex circuit technology memory type s = sram f = flash eeprom e = eeprom d = dynamic ram memory depth, bits pinout options memory width, bits n = x memory speed, ns package type & size surface mount packages thru-hole packages f1 = 1.56"sq 68 lead cqfp p1 = 1.385"sq pga 66 pins f2 = .88"sq 68 lead dual-cavity cqfp p2 = 1.185"sq pga 66 pins f3 = 36 lead fp p3 = 1.075"sq pga 66 pins f4 = 36 lead csoj p4 = 32 pin dip c = commercial temp, 0c to +70c, no 883 screening i = industrial temp, -40c to +85c, no 883 screening t = military temp, -55c to +125c, no 883 screening m = military temp, -55c to +125c, 883 screening q = mil-std-883 compliant screening aeroflex circuit technology 35 south service road plainview new york 11830 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: 1-(800) 843-1553 |
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